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E5550
Standard Read/ Write Identification IC
Description
The E5550 is a contactless R/W-IDentification IC (IDIC)* for general-purpose applications in the 125 kHz range. A single coil, connected to the chip, serves as the IC's power supply and bidirectional communication interface. Coil and chip together form a transponder. The on-chip 264-bit EEPROM (8 blocks 33 bits each) can be read and written blockwise from a base station. The blocks can be protected against overwriting. One block is reserved for setting the operation modes of the IC. Another block can contain a password to prevent unauthorized writing. Reading occurs by damping the coil by an internal load. There are different bitrates and encoding schemes possible. Writing occurs by interrupting the RF field in a special way.
Features
D Low-power, low-voltage CMOS IDIC D Contactless power supply D Contactless read/ write data transmission D Radio Frequency (RF): 100 to 150 kHz D 264 bit EEPROM memory in 8 blocks of 33 bits D 224 bits in 7 blocks of 32 bits are free for user data D Block write protection D Extensive protection against contactless malprogramming of the EEPROM D Typical < 50 ms to write and verify a block D Other options set by EEPROM: Bitrate [bit/s]: RF/8, RF/16, RF/32, RF/40 RF/50, RF/64, RF/100, RF/128 Modulation: BIN, FSK, PSK, Manchester, Biphase ** Other: Terminator mode, Password mode
Transponder Coil interface Power Base station Data
Controller
Memory
E5550
95 10202
Figure 1. Transponder system example using E5550
* **
IDIC stands for IDentification Integrated Circuit and is a trademark of TEMIC Semiconductors Biphase modulation: Terminators not suitable. Terminators proposed in the data sheet well suitable for other modulation modes (e5561A/ TK5561A-PP). If high security level is requested, the e5560B die or TK5560A-PP transponder is recommended for application.
Rev. A4, 25-May-00
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E5550
Ordering Information
Extended Type Number E5550F-DOW Package DOW Remarks
All kind of modulation; RF/8, RF/16, RF/32, RF/40, RF/50, RF/64, RF/100 and RF/128 *) Default programmed: Manchester Modulation, RF/32, MAXBLK = 2
Pads
Chip Dimensions (mm)
Pad Window 136 136 mm2 136 136 mm2 78 78 mm2 78 78 mm2 78 78 78 78 mm2 78 mm2 78 mm2 Function 1st coil pad 2nd coil pad Positive supply voltage Negative supply voltage (gnd) Test pad Test pad Test pad
Y0.22 Coil 1 0.498
AAAAAAAA A A A AAAAAAAA A A A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A AAAAAAAAA A A A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAA A A A AAAAAAAA A A AAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAA AAAAAAAAA
Test1 Test2 Test3
Name Coil1 Coil2 Vdd Vss
0.324
Coil 2 V dd V ss Test pads
2.37 Area = 3.49 mm2
95 10205
E5550 Building Blocks
Analog Front End (AFE)
The AFE includes all circuits which are directly connected to the coil. It generates the IC's power supply and handles the bidirectional data communication with the reader unit. It consists of the following blocks: D Rectifier to generate a dc supply voltage from the ac coil voltage D Clock extractor D Switchable load between Coil1/ Coil2 for data transmission from the IC to the reader unit (read) D Field gap detector for data transmission from the reader unit into the IC (write)
D Handle write data transmission and the write error modes D The first two bits of the write data stream are the OPcode. There are two valid OP-codes (standard and stop) which are decoded by the controller. D In password mode, the 32 bits received after the OPcode are compared with the stored password in block 7.
Bitrate Generator
The bitrate generator can deliver the following bitrates:
RF/8 - RF/16 - RF/32 - RF/40 - RF/50 - RF/64 - RF/100 - RF/128
Write Decoder
Decode the detected gaps during writing. Check if write data stream is valid.
Test Logic
Test circuitry allows rapid programming and verification of the IC during test.
Controller
The main controller has following functions: D Load mode register with mode data from EEPROM block 0 after power-on and also during reading D Control memory access (read, write)
HV Generator
Voltage pump which generates ~18 V for programming of the EEPROM.
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Rev. A4, 25-May-00
1.47
E5550
E5550
Modulator POR
Coil1 Mode register Analog front end Write decoder Memory (264 bit EEPROM) Controller Birate generator Input register
Coil2
Test logic
HV generator
95 10206
Vdd
V ss
Test pads
Figure 2. Block diagram E5550
Power-On Reset (POR)
The power-on reset is a delay reset which is triggered when supply voltage is applied.
Modulator
The modulator consists of several data encoders in two stages, which may be freely combined to obtain the desired modulation. The basic types of modulation are: D PSK: phase shift: 1) every change; 2) every `1'; 3) every rising edge (carrier: fc/2, fc/4 or fc/8) D FSK: 1) f1 = rf/8 f2 = rf/5; 2) f1 = rf/8, f2 = rf/10 D Manchester: rising edge = H; falling edge = L D Biphase: every bit creates a change, a data `H' creates an additional mid-bit change
Mode Register
The mode register stores the mode data from EEPROM block 0. It is continually refreshed at the start of every block. This increases the reliability of the device (if the originally loaded mode information is false, it will be corrected by subsequent refresh cycles).
Carrier frequency PSK1 PSK2 Manchester mux PSK3 mux
From memory
Direct
Direct
to load
Biphase
FSK1, 1a FSK2, 2a
95 10207
Figure 3. Modulator block diagram
Rev. A4, 25-May-00
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E5550
DataClk ReadData PSK1 PSK2 PSK3 f1 = FC/8 FSK1 FSK2 f1 = FC/8 Biphase Manchester
95 10208
1
0
1
1
0
0
1
f2 = FC/5
f2 = FC/10
Figure 4. Types of modulation
Note: The following modulation type combinations will not work: D Stage1 Manchester or Biphase, stage2 psk2, at any psk carrier frequency (because the first stage output frequency is higher than the second stage strobe frequency) D Stage1 Manchester or Biphase and stage2 psk with bitrate = rf/8 and psk carrier frequency = rf/8 (for the same reason as above) D Any stage1 option with any psk for bitrates rf/50 or rf/100 if the psk carrier frequency is not an integer multiple of the bitrate (e.g., br = rf/50, pskcf = rf/4, because 50/4 = 12.5). This is because the psk carrier frequency must maintain constant phase with respect to the bit clock.
Block 1 to 6 are freely programmable. Block 7 may be used as a password. If password protection is not required, it may be used for user data. Bit 0 of every block is the lock bit for that block. Once locked, the block (including the lockbit itself) cannot be field-reprogrammed. Data from the memory is transmitted serially, starting with block 1, bit 1, up to block `MAXBLK', bit 32. `MAXBLK' is a mode parameter set by the user to a value between 0 and 7 (if maxblk=0, only block 0 will be transmitted).
01 L L L L L L L L User data or password User data User data User data User data User data User data Mode data 32 bits Not transmitted
95 10209
32 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0
Memory
The memory of the E5550 is a 264 bit EEPROM, which is arranged in 8 blocks of 33 bits each. All 33 bits of a block, including the lock bit, are programmed simultaneously. The programming voltage is generated on-chip. Block 0 contains the mode data, which are not normally transmitted (see figure 6).
Figure 5. Memory map
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E5550
0 1 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
reserved lock bit (never transmitted)
BR [2] [1] [0]
* "0"
MS1 MS2 PSKCF [1] [0] [2] [1] [0] [1] [0]
MAXBLK * "0" [2] [1] [0] res'd *useSTOP useBT
AOR
useST usePWD
Key: ------------------------------------- AOR Anwer-On-Request useBT use Block Terminator useST use Sequence Terminator usePWD use Password useSTOP obey stop header (active low!) BR Bit Rate MS1 Modulator Stage 1 MS2 Modulator Stage 2 PSKCF PSK Clock Frequency MAXBLK see Maxblock feature reserved do not use * Bit 15 and 24 must always be at "0", otherwise malfunction will appear. 0 0 1 1 0 1 0 1
send blocks: 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 to 2 1 to 3 1 to 4 1 to 5 1 to 6 1 to 7
RF/2 RF/4 RF/8 reserved
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
direct psk1 (phase change when input changes) psk2 (phase change on bitclk if input high) psk3 (phase change on rising edge of input) ----------------------------------- o/p freq. DATA=1 DATA=0 fsk1 rf/8 rf/5 fsk2 rf/8 rf/10 fsk1a rf/5 rf/8 fsk2a rf/10 rf/8
0 0 1 1
0 1 0 1
direct Manchester Biphase reserved
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
RF/8 RF/16 RF/32 RF/40 RF/50 RF/64 RF/100 RF/128
bitrate_8cpb bitrate_16cpb bitrate_32cpb bitrate_40cpb bitrate_50cpb bitrate_64cpb bitrate_100cpb bitrate_128cpb
95 10228
Figure 6. Memory map of block 0
Rev. A4, 25-May-00
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E5550
Operating the E5550
General
The basic functions of the E5550 are: supply IC from the coil, read data from the EEPROM to the reader, write data into the IC and program these data into the EEPROM. Several errors can be detected to protect the memory from being written with the wrong data (see figure 20).
Read
Reading is the default mode after power-on reset. It is done by switching a load between the coil pads on and off. This changes the current through the IC coil, which can be detected from the reader unit.
Start-Up
The many different modes of the E5550 are activated after the first readout of block 0. The modulation is off while block 0 is read. After this set-up time of 256 field clock periods, modulation with the selected mode starts.
Supply
The E5550 is supplied via a tuned LC circuit which is connected to the Coil1 and Coil2 pads. The incoming RF (actually a magnetic field) induces a current into the coil which powers the chip. The on-chip rectifier generates the dc supply voltage (Vdd, Vss pads). Overvoltage protection prevents the IC from damage due to high-field strengths. (Depending on the coil, the open-circuit voltage across the LC circuit can reach more than 100 V). The first occurrence of RF triggers a power-on reset pulse, ensuring a defined start-up state.
Read Datastream
The first block transmitted is block 1. When the last block is reached, reading restarts with block 1. Block 0, which contains mode data, is normally never transmitted. However, the mode register is continuously refreshed with the contents of EEPROM block 0.
Reader coil IAC 125 kHz Energy
Tuned LC
E5550
Data
95 10229
Figure 7. Application circuit
Damping on
Damping off
VCoil1-Coil2
Loading block 0 (256 FCs - 2ms) *
Read data with selected modulation and bitrate
95 10230
Power-on reset
* FCs -> Field clocks Figure 8. Voltage at Coil1/Coil2 after power-on
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E5550
Bit period Block terminator Data bit '1' Block Last bit
Sequence
Last bit VCoil1-Coil2
Waveforms for different modulations
Manchester
FSK
PSK Terminator not suitable for Biphase modulation
13366
No terminators
0
Loading block 0
useST = on useBT = off
0
Loading block 0
useST = off useBT = on
0
Loading block 0 useST = on useBT = on
0
Loading block 0
MAXBLK = 5
0
Loading block 0 MAXBLK = 2 0 Block 1 Block 2 Block 1 Block 2 Block 1
Loading block 0
MAXBLK = 0
0
Loading block 0
Rev. A4, 25-May-00
IIIIIIIIIIIII II I III II II I I IIIIIIIIIIIIIIIIIIIII III I I II I IIIIIIIII I III II II I III IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII II II III IIIIIIIII IIII II I I I I IIIIIIIIIIIIIIIIIIII IIIIIIIII IIIII II I II IIII I I II I I IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I II
Block 1
Block 1
Block 1
Block 0
IIIII IIIII IIIII IIIII
First bit Sequence terminator Data bit '1' Data bit '1'
First bit First bit '0' or '1'
Figure 9. Terminators
Block 2
Block 7
Block 1
Block 2
Sequence terminator
Block 1IIIII Block 2
Block 7
Block 1
Block 2
Block terminator
Block 2
Block 7
Block 1
Block 2
Block 1
Block 2
Block 7
Block 1
Block 2
95 10232
Figure 10. Read data streams and terminators
Block 4
Block 5
Block 1
Block 2
Block 0
Block 0
Block 0
Block 0
95 10233
Figure 11. MAXBLK examples
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E5550
Terminators
The terminators are (optionally selectable) special damping patterns, which may be used to synchronize the reader. There are two types available; a block terminator which precedes every block, and a sequence terminator which always follows the last block. The sequence terminator consists of two consecutive block terminators. The terminators may be individually enabled with the mode bits useST (sequence terminator enable) or useBT (block terminator enable). Note: It is not possible to include a sequence terminator in a transmission where MAXBLK = 0. block by sending the write OP-code, the lock-bit and the 3-bit address. This does not work in password-mode.
Modulation and Bitrate
There are two modulators in the E5550 (see figure 3) whose mode can be selected using the appropriate bits in block 0 (MS1[1:0] and MS[2:0]). Also the bitrate can be selected using BR[2:0] in block 0. These options are described in detail in figure 6.
Maxblock Feature
If it is not necessary to read all six user data blocks; the MAXBLK field in block 0 can be used to limit the number of blocks read. For example, if MAXBLK = 4, the E5550 repeatedly reads and transmits only blocks 1 to 4. If MAXBLK is set to `0', block 0 (which is normally hidden) is read.
Direct Access
Direct access is a feature for reading out an individual
Modulation on VCoil1-Coil2
Loading block 0 POR
No modulation Standard OP-code followed by valid password 95 10234 because AOR=H
Figure 12. Answer-on-request mode
>64 FCs = stop write RF_Field gap write mode Modulation during ReadMode damping write data Data Clock field clock readmode writing
Figure 13. Signals during writing
Start
1
0
1
1
0
Load On
Load Off
programming readmode
95 11378
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Rev. A4, 25-May-00
E5550
1 Write data decoder fail 16 0 32 fail 48 1 64 writing done
95 10236
Figure 14. Write data decoding schemes
Standard write Password mode AOR wake up Stop modulation
OP 10 L 1 OP 10 1 OP 10 OP 11
Data bits Password Password 32 L 1
32 2 ADR 0 Data bits 32 2 ADR 0
9510237
Figure 15. Legal write data sequences
Write
Writing data into the IC occurs via the TEMIC write method. It is based on interrupting the RF field with short gaps. The time between two gaps encodes the `0/1' information to be transmitted.
write mode; it starts with programming if the correct number of valid bits were received. If there is a gap fail - i.e., one or more of the gaps was not a valid `0' or `1' - the IC does not program, but enters read mode beginning with block 1.
Start Gap
The first gap is the start gap which triggers write mode. In write mode, the damping is permanently enabled which eases gap detection. The start gap may need to be longer than subsequent gaps in order to be detected reliably. A start gap will be detected at any time after block 0 has been read (field-on plus approximately 2 ms). Read mode RF Start of writing (start gap)
Figure 16. Start of writing
Writing Data into the E5550
The E5550 expects always to receive a OP-code first. This OP-code may be followed by different information: D Standard writing needs only the OP-code, the lock bit, the 32 data bits and the block address. D Writing with usePWD set requires a valid password between OP-code and address/data bits. D In AOR mode with use PWD, OP-code and a valid password are necessary to enable modulation. D A special OP-code is used to silence the E5550 (disable damping until power is cycled). Note: The data bits are read in the same order as written.
Write mode
OP-Codes
There are two valid OP-codes. If the OP-code is invalid, the E5550 starts read mode beginning with block 1 after the last gap. The standard OP-code (`10') precedes all write operations. The stop OP-code (`11') is used to stop the IC until a power-on reset occurs. This feature can be used to have a steady RF field where single transponders are collected one by one. Each IC is read and than disabled, so that it does not interfere with the next IC.
95 10238
Decoder
The duration of the gaps is usually 50 to 150 ms. The time between two gaps is nominally 24 field clocks for a `0' and 56 field clocks for a `1'. When there is no gap for more than 64 field clocks after previous gap, the IDIC exits
Rev. A4, 25-May-00
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E5550
Note: The stop OP-code should contain only the two OPcode bits to disable the IC. Any additional data sent will not be ignored, and the IC will not stop modulation. Standard OP-code 1 Start gap Stop OP-code 1 1 > 64 clocks 0 more data ... D If usePWD is not set, but the IC receives a write datastream containing any 32 bits in place of a password, the IC will enter programming mode. D The first 4 bits of the password have to be "0". D In password mode, MAXBLK should be set to a value below 7 to prevent the password from being transmitted by the E5550.
95 10239
They are compared bit-by-bit with the contents of block 7, starting at bit 1. If the comparison fails, the IC will not program the memory, but restart in read mode at block 1 once writing has completed. Notes:
Read mode
Write mode
Figure 17. OP-codes
Password
When password mode is on (usePWD = 1), the first 32 bits after the OP-Code are regarded as the password.
D Every transmission of 2 OP-code bits plus 32 bits password plus 3 bits address plus 33 bits data (= 70 bits) needs about 35 ms. Testing all 232 possible combinations (about 4.3 billion) takes about 40,000 h, or over four years. This is a sufficient password protection for a general-purpose IDIC.
Writing done (> 64 clocks since last gap) Write mode Programming ends Check V pp 16 ms 0.12 ms Programming starts (HV at EEPROMs) Reading starts
HV on HV on for testing if Vpp is ok Modulation No modulation
Operation
Write
Vpp/Lock ok?
Program EEPROM
READ
95 10240
Figure 18. Programming
VCoil1-Coil2 16 ms programming Read programming block (= block 0) Read next block with updated modes (e.g., new bitrate)
95 10241
Write data into the IC
Figure 19. Coil voltage after programming of Block 0
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Rev. A4, 25-May-00
E5550
Programming
When all necessary information has been written to the E5550, programming may proceed. There is a 32-clock delay between the end of writing and the start of programming. During this time, Vpp - the EEPROM programming voltage - is measured and the lock bit for the block to be programmed is examined. Further, Vpp is continually monitored throughout the programming cycle. If at any time Vpp is too low, the chip enters read mode immediately. The programming time is 16 ms. After programming is done, the E5550 enters read mode, starting with the block just programmed. If either block or sequence terminators are enabled, the block is preceded by a block terminator. If the mode register (block 0) has been reprogrammed, the new mode will be activated after the just-programmed block has been transmitted using the old mode. D Wrong number of field clocks between two gaps D The OP-Code is neither the standard OP-Code nor the stop OP-Code D Password mode is active but the password does not match the contents of block 7 D The number of bits received is incorrect; valid bit counts are D Standard write D AOR request 38 bits (usePWD not set) D Password write 70 bits (usePWD set) 34 bits D Stop command 2 bits If any of these four conditions are detected, the IC starts read mode immediately after leaving write mode. Reading starts with block 1.
Errors During Programming
If writing was successful, the following errors could prevent programming: D The lock bit of the addressed block is set D VPP is too low In these cases, programming stops immediately. The IC reverts to read mode, starting with the currently addressed block.
Error Handling
Several error conditions can be detected to ensure that only valid bits are programmed into the EEPROM. There are two error types, which lead to two different actions.
Errors During Writing
There are four detectable errors which could occur during writing data into the E5550:
Power-on reset Set modes
READ Write mode 11 OP-code ok 10 Password adr=1 fail fail fail fail fail fail
95 10243
adr=current
Stop
ok Number of bits ok Lock bit ok HV ok PROGRAM ok Figure 20. Functional diagram of the E5550
Rev. A4, 25-May-00
11 (14)
E5550
Absolute Maximum Ratings
Parameters Maximum DC current into COIL1/COIL2 Maximum AC current into COIL1/COIL2 f = 125 kHz Power dissipation (dice) 1) Electro-static discharge maximum to MIL-Standard 883 C method 3015 Operating ambient temperature range Storage temperature range 2) Maximum assembly temperature for less than 5 min 3) Notes: 1) 2) 3) Symbol Icoil icoil pp Ptot Vmax Tamb Tstg Tsld Value 10 20 100 1000 -40 to +85 -40 to +125 +150 Unit mA mA mW V C C C
Free-air condition, time of application: 1 s Data retention reduced Assembly temperature of 150C for less than 5 minutes does not affect the data retention.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Operating Characteristics
Tamb = 25C; fRF = 125 kHz, reference terminal is VSS
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5 100 7.5 200 mA mA V V Clamp voltage Programming voltage Programming time Startup time Data retention Programming cycles Supply voltage Supply voltage Coil voltage Coil voltage Damping resistor 11.5 20 18 4 ms ms Years V V V V 1.6 2.0 6.0 10 300 W Note 1) Since EEPROM performance may be influenced by assembly and packaging, we can confirm the parameters for dow (= die-on-wafer) and ICs assembled in standard package. 12 (14) Rev. A4, 25-May-00
Parameters RF frequency range Supply current
Symbol Min. fRF 100 Read and write over the full fullAAAA temperature range IDD Programming over the full IDD temperature range 10 mA current into Coil1/2 Vcl 9.5 From on-chip HVVpp 16 Generator tP tstartup 1) tretention 10 1) ncycle 100 000 Read and write VDD Read-mode, T = - 30C VDD Read and write Vcoil pp Programming, Vcoil pp RF field not damped RD
Comments
Typ. 125
Max. 150
Unit kHz
E5550
IDD VDD Coil 1
Coil 1 100 W ~2V
~
Coil 2 VSS Vpp Coil 1.5 V
=
2V
Coil 2 100 W ~2V
Mod
96 12304 96 12303
Figure 21. Measurement setup for IDD
Figure 22. Simplified damping circuit
Application Example
From oscillator IAC 125 kHz 740 mH Energy 4.2 mH 360 pF
E5550
To read amplifier Data
fres + 2.2 nF Figure 23. Typical application circuit
1 + 125 kHz 2p LC
Rev. A4, 25-May-00
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E5550
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
1.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.temic-semi.com
TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
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